- Prof. Dr. Sezer Gören Uğurdağ
- Abdullah Yıldız
- Cemil Cem Gürsoy
Recently, multi-cycle tests that offer high test quality have been proposed. Multi-cycle tests are accomplished by feeding the input vector constantly and putting the circuit in functional mode for multiple cycles. Multi-cycle tests are often needed by partial-scan circuits and circuits with multiple clock-domains. In addition, the VLSI Test community is interested in multi-cycle tests because of the fact that they can reduce the test time and cost by detecting more faults with the same test vector. However, the fault simulation of multi-cycle tests is very computationally expensive. In literature, no fault emulation method for multi-cycle tests has been proposed yet. In this project, our aim is to develop a fault emulation method for multi-cycle tests. With the help of our fault emulation method, we accelerate the process of fault simulation of multi-cycle tests.
START: 2014
END: 2016
ID: 114E022
FUNDING INSTITUTION: TÜBİTAK
BUDGET: 72843
STATUS: Completed